A conventional parallel to serial data transfer system includes a CPU (central processing unit) for supplying parallel data of one byte at a time, a buffer connected to the CPU for storing the parallel data transferred from the CPU, and a parallel to serial shift resister connected to the buffer for converting parallel data to serial data.
In operation, when a write request-signal is supplied to the CPU, parallel data of one byte is transferred from the CPU to the buffer. Then, the parallel data is loaded from the buffer to the parallel to serial shift resister. After that, the parallel data of one byte loaded in the shift resister is read therefrom one bit by one bit in synchronism with a clock signal. Thus, the parallel data are converted to serial data.
According to the conventional parallel to serial data transfer system, however, there are disadvantages in that the lead of the CPU becomes large, because the CPU has to access the buffer every time one byte is transferred in response to the write request signal, so that the CPU has to access the buffer "m" times in the case of the data transfer of "m" bytes. Further, if the buffer has a memory capacity of "n" bytes more than "m" bytes of parallel data transferred from the CPU, the "n-m" bytes has to be filled with dummy data, so that the lead of the CPU becomes larger.